Artificial intelligence (AI) is one of the most transformative technologies of our time, driving unprecedented demands on networking infrastructure to provide significantly higher data rates to support a tremendous amount of computational and informational traffic needed for training and inference. This has led to a significant increase in demand for optical interconnects that are able to support the increasing speeds required for AI networking infrastructure.
While optical interconnects provide the necessary bandwidth to support high data rates, the critical factors for the network infrastructure are the reliability and robustness of these optical interconnects to ensure consistent, error-free data transmission. AI training involves highly parallel, batch-based computation. A link error on any of the interconnects is very impactful as the batch must be restarted, and the downtime during this restart and rerun process translates into a significant cost in money and productivity. From an inference perspective, errors can cause increased latency when delivering results. While not as impactful as in training mode, errors contribute to increased inference inefficiencies.
To ensure an error free optical interconnect, there must be sufficient link margin to ensure that even in corner-case environments the link is robust enough to withstand any stressors. In addition, due to the high-density environment of an AI networking infrastructure, it is important that the optical interconnect’s power consumption is kept to a minimum.
The sheer scale of AI’s growth means that existing optical interconnect suppliers, even with expanded capacity, may struggle to meet future demand. Vendor diversity will be essential to ensure the market can keep pace with the exponential increase in data center bandwidth requirements, which are projected to grow 6x by 2030 due to AI, according to LightCounting. As these devices continue to proliferate the market, vendors involved in the optical interconnect supply chain are seeing a tremendous opportunity for growth and expansion by focusing on solutions that prioritize robust, dependable connectivity alongside bandwidth capacity.
Key Optical Interconnect Components
A key optical interconnect component found in today’s AI networking infrastructure is the four-level pulse amplitude modulation (PAM4) digital signal processor (DSP) application specific integrated circuit (ASIC) which doubles the bit rate of short reach optical interconnects compared to traditional two-level non-return-to-zero (NRZ) transmission methods. While current PAM4 implementations are already a challenge due to DSP and high-speed RF complexity to implement an error-free multi-level link (maintaining a clean eye-diagram opening for three stacked eyes versus one eye in the case of NRZ), moving towards next generation higher speed requirements poses even more challenges. The required sophisticated digital equalization techniques and other signal integrity implementations for higher PAM4 speeds increase DSP complexity.
Higher speed optical interconnects have led to increased adoption of silicon photonics (SiPh) integrated circuit technology as the higher bandwidths are more challenging for directly modulated lasers. Laser-based light can be manipulated at very high speeds inside SiPh optical waveguide circuits with support from high-speed RF analog components that translate the electrical signals from the DSP ASIC to the SiPh modulator and vice versa. This combination of the SiPh and the supporting RF components are typically referred to as optical engines. SiPh provides the advantages of temperature insensitivity and the utilization of mature volume manufacturing processes used in the electronics industry. This has resulted in increased quality and reliability of optical interconnects.
Today’s 800G Implementations Moving to 1.6T
The current generation of I/O ports support an optical interconnect speed of 800G, with PAM4 DSPs and optical engines housed in pluggable client optics modules in QSFP-DD or OSFP form factors. These modules are plugged directly into switch, router, and network interface card (NIC) ports that connect to host electrical interfaces operating at speeds of 100G per lane widely deployed today.
For this scenario, the host electrical signals at 100G per lane using eight electrical lanes pass through an electrical connector into a client optics module connecting to the internal PAM4 DSP. The PAM4 DSP, followed by the optical engine, converts the eight 100G electrical signals into the four-level optical signal that is then transmitted over a single-mode fiber. At the receiving end, a client optics receiver converts the received four-level optical signal back to eight 100G electrical signals on the receiving host port.
The demand for increased optical interconnect speeds is accelerating the transition to the next generation of 1.6T client optics modules. LightCounting is forecasting sales of 1.6T Ethernet optical transceivers to begin ramping in 2026, and to exceed $15 billion by 2030.
The implementation of these modules is similar to the 800G versions with the electrical host signals rising to 200G-per-lane speeds. Availability of 3nm CMOS silicon has enabled 200G-per-lane bit rates utilizing complex algorithms reliably implemented in high-transistor-count, low-power consuming silicon ASICs.
Supplier Expansion Requires Experience and Reliability
Reliance on PAM4 DSP functionality will continue to grow as client optics demand increases due to the expansive buildouts of AI networking infrastructure. It will also be critical as the required optical interconnect speeds increase from 800G to 1.6T with an aggressive ramp planned as illustrated in the LightCounting forecast above. The growth trajectory over this time emphasizes how critical it will be to have numerous PAM4 DSP suppliers to support this growth by providing high volume, high quality, and reliable components.
These suppliers not only need to have the ability to support high-volume production, but they should also have experience with DSP and high-speed RF design to mitigate both electrical and optical data link issues to ensure extremely robust and reliable high-speed connectivity.
Leveraging its proven DSP expertise and high-volume capabilities, Acacia introduced Kibo, a 3nm 1.6T PAM4 DSP ASIC designed to power the optical interconnects inside AI data centers. The Kibo PAM4 DSP, in conjunction with Acacia’s Optical Engine products, can deliver a solution with the performance and power efficiency required for even the most demanding AI workloads.
Enabling 20 Percent Lower Power with Client Optics Technology
The 3nm CMOS node design of Kibo provides impressive power efficiency that enables more than 20% lower power compared to existing 1.6T module implementations. Kibo also supports Transmit Retimed Optics (TRO) configurations with power-efficient support for diagnostic and loopback troubleshooting capabilities, as well as support for electrical gearbox and retimer applications. Designed for OSFP/QSFP-DD form-factor modules, Kibo supports 1.6T DR8 and 2xFR4; 800G DR4/DR8/FR4, and 2xFR4.
The expansion of AI networks is fundamentally reshaping the demands on our networking infrastructure, making high-bandwidth optical interconnects indispensable. Critical components such as PAM4 DSPs will require a robust supply chain that can provide the high-volume, high-quality, and highly reliable components necessary to meet the growth of optical interconnects for AI networks.
To learn more about Acacia’s Kibo DSP and Optical Engines, contact us.
